Many IC devices, such as, for example, complementary metal-oxide semiconductor (CMOS) devices, are formed comprising a plurality of essentially identical repeated circuit cells, such as, for example, a static random access memory (SRAM) array. As CMOS fabrication technologies advance, SRAM can remain a primary mechanism for affording logic-compatible, high-speed embedded nonvolatile memory, provided corresponding improvements in SRAM cell packing density can be achieved. In order to improve packing density, full scaling of all critical dimensions in the SRAM cell is generally required, which poses significant challenges in process integration, especially in lithography patterning techniques. These challenges include both the resolution of small features as well as the controllability of critical dimensions from device to device, or from wafer to wafer. Such process variations can affect one or more characteristics of the device, including, but not limited to, device threshold voltage, which can severely degrade device yield and/or stability, particularly at reduced power supply voltages. Additionally, it becomes increasing more difficult to fabricate complex geometries in the IC device as dimensions are reduced. Consequently, devices are preferably formed using Manhattan (e.g., x-y) coordinates.
In recent years, there has been a transition from device designs utilizing completely arbitrary pattern sizes and orientations to semi-constrained designs, especially relating to memory design. Semi-constrained designs typically involve maintaining a substantially fixed gate pattern pitch throughout the device. However, gate length is not always fixed. Furthermore, active regions (e.g., source and drain regions) in these devices use varied line dimensions and line spacings, as described, for example, in U.S. Pat. No. 6,534,805 to Jin, the disclosure of which is incorporated by reference herein. Consequently, full scaling of such devices, so as to benefit from shrinking process dimensions, is not easily attainable.
There exists a need, therefore, for a semiconductor design methodology suitable for use, for example, in an SRAM array, which does not suffer from one or more of the above-noted deficiencies associated with conventional semiconductor design approaches.